In modern communications, the phase-locked loop (PLL) based frequency synthesizer is an important building block for frequency translation. The high-speed prescaler and the voltage-controlled oscillator (VCO) are the most critical components in a frequency synthesizer. Although they are usually implemented in bipolar or GaAs technologies before, advanced standard CMOS technology has been widely used to design such circuits for the several years in order to realize the single-chip RF-to-baseband systems.
The prescaler is a high-speed digital frequency divider, and one of the important design goals of the circuit is low power consumption for the battery-operated portable applications. For CMOS digital circuits, the dynamic dissipation power is proportional to the square of supply voltage and thus the goal can be efficiently achieved by lowering the supply voltage. For example, Nippon Precision Circuits Inc. datasheet, xe2x80x9cSM5160CM/DMxe2x80x9d disclosed a 1 V frequency synthesizer implemented in special CMOS process has been used for pager systems.
However, further reduction in threshold voltage is not easy because of the exponentially increasing subthreshold current. For example, the typical threshold voltages of the NMOS and PMOS transistors in the technology we use are 0.55 V and 0.7 V respectively. Thus, the operating speed of low-voltage digital circuits will be limited.
Recently, Ming -Jer Chen et al. disclosed a novel back-gate forward bias (BGFB) scheme which has been introduced as an efficient trade-off between operating speed and subthreshold leakage current [IEEE Transactions on electron devices, vol. 43, no. 6, pp. 904-909, Jun. 1996]. This circuit technique can be used in present standard bulk CMOS processes to reduce the threshold voltage electrically without any mask or process modifications.
In this invention, a new low-voltage inverter and DFFs using the xe2x80x9cdynamicxe2x80x9d BGFB method are presented. A 1 V dual-modulus prescaler using the proposed DFFs has been fabricated in a standard 0.35 xcexcm CMOS technology. The maximum operating frequency of 170 MHz has been measured at 1 V supply voltage.
In this invention a low-voltage divide-by-64/65 prescaler fabricated with a 0.35xe2x88x92xcexcm standard CMOS technology is presented to lower power dissipation. A new dynamic D-flip-flop (DFF) using the dynamic back-gate forward bias method has been developed for low-voltage operation. The prescaler including a preamplifier measured at 1 V supply voltage has a maximum operating frequency of 170 MHz and its power dissipation is only 0.9mW.